TUSB1210-Q1 data sheet, product information and support | TI.com
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
USB 3.0 PHY for SoC Designs | Cadence IP
Canovatech - CT25201_PHY
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
The USB 2.0 Device IP core | Arasan Chip Systems
Hi-Speed USB interfacing
The Next-Generation Interconnect | Mouser
USBPHYC internal peripheral - stm32mpu
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
USB 2.0 PHY for SoC Designs | Cadence IP
Confidently Characterize Validate and Debug Your USB 31 Electrical PHY Designs | Tektronix
USB PHY芯片 | 码农家园
HSIC USB 2.0 PHY IP
Difference between USB and ULPI - Electrical Engineering Stack Exchange
USB 2.0 Device Controller for SoC Designs | Cadence IP
ULPI - Kcchao
Canovatech - CT20602
Having trouble getting USB PHY to work with STM32 : r/embedded
Mixed-Signal Verification for USB 2.0 Physical Layer IP
USB Device
